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Tutorial 1 
Virtual Reliability Qualification and Reliability Assessment of Microelectronics - Towards short-time-to-market and cost reduction (4h)

G.Q. Zhang
Technical University of Eindhoven and Philips Centre of Industrial Technology, The Netherlands
g.q.zhang@philips.com

Course Description

The rapid technological development trends of microelectronics and Microsystems are mainly characterized by miniaturization down to nano-scale, increasing levels of technology and function integration and eco-design, while the business trends are mainly characterized by cost reduction, short-time-to-market and outsourcing. These trends lead to increased chances and consequences of failures, increased design complexity, decreased product development and qualification times, dramatically decreased design margins and increased difficulties to meet quality, robustness and reliability requirements. To achieve competitive product/process development and manufacturing excellence, it is vital and a must to know and to apply the state-of-the-art methods for virtual reliability qualification and reliability assessment.

Content & scope

1. Development trends of Microelectronics and Microsystems
2. Status quo of reliability qualification and assessment 
3. The state-of-the-art of virtual reliability qualification (i.e., designing for reliability), including the basic theories and methodologies
4. Case study of virtual reliability qualification covering typical failure modes related with wafer backend, IC packaging and board level assembly, such as (not limited to)
   - Various cracks
   - Delamination
   - Wire bonding failures
   - Solder fatigues
   - Moisture induced failures
   - Warpage, etc.
5. Challenges and future perspectives 

This half-day course provides the participants with a unique chance to learn both the overview on the state-of-the-art methodologies, and the detailed ways of working & applications via case studies. The added business values/per case will also be demonstrated. It is strongly recommended to you to email your wishes and problems to the instructor 2 weeks earlier, so that this course can be tailored to some of your specific wishes and to help you to find the solutions for your concrete problems.

Who Should Attend

Microelectronics design engineers, reliability engineers, product/process developers and managers, thermal and mechanical analysts, researchers, graduates, PhD students and postdoc.

About the Instructor

Beside his responsibilities in Technical University of Eindhoven, Prof. Zhang is also a principal scientist and competence leader at Philips Centre For Industrial Technology, The Netherlands.
Prof. Zhang is author and co-author for more than 80 scientific publications, including journal and conference papers, book and invited keynote lectures. He is the general chair of international conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) and committee/executive member of several international conferences (such as ECTC, EPTC, ICEPT, MicroMat) and academic societies (such as IMAPS Benelux, IEEE-CPMT). He is leading some related R&D activities and initiatives in Europe.
His scientific interests include virtual prototyping and virtual qualification, development of fundamental and application knowledge of computational & experimental mechanics, advanced optimization methods and reliability engineering, and especially their applications in microelectronics, Microsystems and nanotechnology.

Cancelled: Tutorial 2
Thin Chip Preparation, Separation, Handling and Assembly as well as an Outlook on Thin Chip Systems Integration (4h)

Thinning, Dicing, Handling and Assembly Processes for Thin Chips as Integrated Approach to be applied in the development of flexible or highly integrated electronic systems, but also for high-volume small chip products on large wafer size

Karlheinz Bock
Fraunhofer Institute for Reliability and Microintegration (IZM), Germany

Course Description

The Tutorial introduces an integrated thin chip process. Thinning, Dicing, Handling and Assembly Processes for Thin Chips have to be developed together in an Optimised and Integrated Approach. This approach starts from the thinning of product wafers, contends related chip separation techniques and extends to handling techniques and the assembling processes needed to bring the thin chip safely into the product and to allow for a reliable operation. 

After an introduction to thin chip applications the tutorial focuses on the development of thinning processes and explains the different thinning techniques applied. In a strong correlation the wafer carrier and handling as well as the wafer preparation is described in detail. In a further part the correlated assembly processes are presented in a relation to possible product or application scenarios. Thin chip reliability and corresponding analysis methods will also be covered in detail. 

The choice of a thinning process in many cases already defines the boundary conditions of the separation handling or assembly process of a product. Therefore having the product in view none of the processes can be developed in an isolated manner. The tutorial will also show the limited requirements needed to be changed in the fabrication chain of silicon chip products in order to apply the integrated thin chip process in full extend.

The tutorial finishes with an outlook on thin chip packaging and integration techniques and the introduction of reel-to-reel processing of systems with thin chips and manufacturing of low-cost thin chip products in a reel-to-reel application centre.

Keywords: Thinning, Grinding, spin etching, wet chemical etching, CMP, chemo-mechanical polishing, cleaning, lamination, carrier, adhesives, ICA, NCA, ACA, flip-chip assembly, iso-planar interconnect, 3D-integration, chip on flexible substrates, reel-to-reel processing, polymer electronics, wearables, wearable computing, flexible electronic assemblies, cubic or 3D-integration of CMOS, pervasive and ubiquitous computing, polytronics.

Who Should Attend

The tutorial addresses engineers, product designers and managers involved with silicon front- and backend technology, design, packaging and assembly and the production of electronic devices and systems. There will be overview but also detailed information provided. The tutorial will also show advantages of thin chips and some possible influences to the product development and its functionality and pricing. The tutorial will cover present possible and future applications of thin silicon dies, referring to applications like stacked die thin packages or chips integrated in mechanics or cloths (wearables, wearable computing, flexible electronic assemblies, cubic or 3D-integration of CMOS, pervasive and ubiquitous computing).

About the Instructor

Dr. Bock studied electronics and communication engineering at the University of Saarbrücken, Germany. From October 1986 to September 1987 he has been a scientific assistant at the Institute for Material Science Saarbrücken, Germany where he was involved in Mössbauer spectroscopy on laser treated metal surfaces. From September 1987 to March 1989 he has been employed as a technical consultant. From September 1989 to March 1994 he has been employed at the University of Darmstadt, Germany as research assistant and doctoral student on the subject of high-frequency communication microelectronics technology and reliability. In 1994 he has been promoted the Dr.-Ing. Degree in RF microelectronics. From August 1994 to August 1995 he has been Japan Society for the Promotion of Science Award (JSPS) invited post-doctoral researcher at the Tohoku University, Japan working on the development of strained SiGe CVD layer growth and corresponding RT-diode devices technology and characterization. From September 1995 to March 1996 he again joined the University of Darmstadt, Germany, Institute of high-frequency communications working in RF HT mechatronics. From March 1996 July 1999 he has been employed at IMECvzw in Leuven, Belgium working on deep-submicron CMOS technology, ESD reliability. From 1999 – 2000 he joined the Fraunhofer Management Gesellschaft in Munich, Germany as business director, Information and Communication technologies. Since January 2001-present he is employed at the Institute for Reliability and Microintegration in Munich, Germany as head of the Polytronic Systems Department working on the development of thin and flexible systems technologies.

Tutorial 3
Design, Optimization, Process and Analysis of RF-Modules in LTCC (4h)

Peter Uhlig and Jürgen Kassner
IMST, Germany

Course Description

LTCC as a ceramic multilayer technology has a great potential for Microwave applications. The dielectrics (tapes) as well as the gold and silver conductors have the appropriate physical and electrical performance. In spite of being a very mature technology, LTCC has recently gone through large improvements in material development and has become available for communication equipment manufacturers through LTCC foundries. The competitive price of materials and production make LTCC an ideal basis for System in a Package (SiP) and Multi Chip Modules (MCM). LTCC circuits can consist of a nearly arbitrary number of layers. Components can be integrated in cavities. LTCC substrates are rugged, hermetic and environmentally stable. These features and further favourable characteristics are utilized to develop compact and efficient modules for communication and sensor applications. This tutorial is intended to give the participants an understanding of the basics for a successful design and production of LTCC modules for microwave and RF applications.

Unit 1: Survey of LTCC Material Systems and Manufacturers
From a microwave point of view the exchangeability of LTCC systems is somewhat limited. This survey will help to identify potential material systems, manufacturers of LTCC circuits and second sources in an early stage of development. This information is particularly interesting for companies looking for production facilities to launch their own products and applications.

Unit 2: LTCC Process
All the LTCC process steps from tape casting to sintering will be explained. Different process alternatives will be introduced and discussed. A basic understanding of the relevance of these parameters helps to understand design rules and is essential for a successful design. 

Unit 3: Applications in Telecommunication and Sensor Electronics 
These applications will include elements like waveguides, transitions, filters, antennas and other passive components. The embedding of active circuits will be demonstrated on an amplifier. LTCC-Bluetooth-Modules and two complete TX/RX-modules will be discussed to show virtues and opportunities as well as challenges of the LTCC-Technology.

Unit 4: 3D-Simulation and Test methods
Multilayer RF modules demand sophisticated simulation tools to take the guesswork out of the design process. The analysis of 3-dimensional structures is accomplished by very elaborate procedures. Commercially available software will be introduced and demonstrated as device for the design of multi layered structures. This includes preparation and checking of artwork. A high level of automation is desirable to avoid errors transferring the design to production. Finally a method of benchmarking the RF-performance of LTCC material systems is explained.

Who Should Attend?

The tutorial is dedicated to engineers working in the development of RF and high frequency modules. It will give managers an understanding of this technology.

About the Instructors

Jürgen Kassner received the diploma degree in electrical engineering from the University of Ulm, in 1996. 1996-1999 he was research assistant at the University of Ulm in the division of microwave techniques. There he worked in the area of interconnects and packaging on multi-layer LTCC. He was given the Dr.-Ing. degree from the University of Ulm, in 2000. In 1999 he joined the IMST GmbH in Kamp-Lintfort, Germany. Since then he works in the subdivision of RF Modules in the RF Circuits and Systems department. His respective design activities cover 2D- and 3D circuit development in the mm-wave frequency range. He is engaged in research activities for power distribution networks for antennas, waveguide interconnects, and communication systems. His areas of interest are ceramics multi-layer substrates, active and passive circuit design, mm-wave interconnects, and system aspects. 

Peter Uhlig received his degree in electrical engineering in 1984. At Wandel & Goltermann he started 1984 with the development of microwave components for spectrum analysers. From 1988 on he was responsible for the thin film circuits of the microwave front-end in these instruments. He joined IMST GmbH in 1993 where he is heading the hybrid microelectronics laboratory which includes the LTCC prototyping line.

Tutorial 4
Ambient Intelligence and Embedding Components - Application Viewpoints (4h)

Dr. Kieran Delaney
NMRC Institute, National University of Ireland – Cork,
Lee Maltings, Prospect Row, Cork, Ireland
kieran.delaney@nmrc.ie
www.nmrc.ie

Course Description

This new tutorial examines the novel research area of Ambient Intelligence and Ambient Electronics Systems. 
The future of information technology systems will be driven by the vision of Ambient Intelligence.
In this vision, Ambient Intelligence will surround us with proactive interfaces supported by computing and networking technology platforms that are everywhere; for instance, its systems would be embedded into everyday objects such as furniture, clothes, vehicles, roads and even in decorative materials like paint, wallpaper, etc. They would be unobtrusive, often invisible. They will provide a seamless environment of computing, advanced networking technology and specific interfaces. The systems will be aware of the specific characteristics of human presence and personalities, and will take care of needs. It will be capable of responding intelligently to spoken or gestured indications of desire, and could engage in intelligent dialogue. Interacting with ambient intelligence would be relaxing and enjoyable for the citizen, and not involve steep learning curves. Developing such systems requires a convergence of technology innovation at all levels; this extends from sensors through hardware and software to intuitive user interfaces. The scope of this is such that the entire focus of pan-European information systems technology research will focus upon its development in the next 5-year period.

The scope of the tutorial will cover the definition and history of Ambient Intelligence, current active programs, the multidisciplinary approach, and guidelines for future research and development. In addition, we will address applications issues, including requirements and challenges for the interconnection and systems packaging research community.

Ambient Intelligence (AmI)

• A Historical Perspective
• Current Research Thrusts Worldwide
• AmI Road maps
• Requirements for Multidisciplinary

Research Strands

• The “Disappearing Computer”
• Interactive User Design: the “Nature-to-Nurture” Approach
• Mobility, Context Awareness, and Localisation
• Information Flow – Perception and Interfacing

Applications

• Ambient Intelligence: Arguments for and against
• Techno-economic obstacles and opportunities
• Psychosocial obstacles and opportunities
• Methodology for implementation

Systems Approaches to Ambient Intelligence

• Hardware Systems Platforms
• Systemic Augmentation of Everyday Objects
• Scalable Sensing and Actuation
• Hardware Systems Roadmaps and Research Thrusts

About the Instructors

Dr. Kieran Delaney received B.E. (Elec.) and PhD. degrees from University College Cork, Ireland in 1992, and 1997, respectively. In his doctoral work, he developed characterisation techniques and predictive models for Integral Capacitors and Resistors in LTCC Substrates. He joined the Interconnection and Packaging Group in the NMRC in 1996 as a Research Scientist, where his responsibilities included coordinating the NMRC's role in evaluating novel interconnection technologies in a number of multinational European projects. In 1999, he was appointed to the position of Technology Manager within the Microelectronics Applications Integration Group at NMRC with responsibility for Microelectronics Packaging in the areas of technology development, characterisation and reliability. His current responsibilities include managing the research and development activities of emerging hardware technology platforms in the novel research area of Ambient Electronic Systems.

Tutorial 5
Lead-Free Electronics – Materials, Assembly and Reliability (2.5h)

MSc. Toni Mattila, Ph.D. Tomi Laurila and Prof. Jorma Kivilahti

Venue: The Lab. of Electronics Production Technology, HUT, Otakaari 7B, Hall ST1

Course Description

The adoption of lead-free solder fillers, component and board metallizations together with decreasing solder joint volumes of electronic components such as BGAs, CSPs and Flip Chips increase the complexity of solder metallurgies, and thereby create new challenges for the manufacturing and reliability of electronics. 

The objectives of the course are to provide the attendees good background in lead-free solder material properties, to deal with new design and manufacturing requirements and consider the metallurgical compatibility of lead-free solders, component metallizations and PWB finishes from the manufacturing and reliability points of view. 

Topics covered

• Lead-free solder materials – properties, availability and patent issues
• Technological issues in lead-free soldering - Pb-free component metallizations, Pb-free PCB surface finishes and Pb-free reflow process key criteria 
• General reliability issues in lead-free electronics
• Differentiation of solder joint failure modes between SnPb- and Pb-free assemblies
• Interfacial metallurgy and interconnection reliability

Who Should Attend?

The course will benefit those who are interested in the development and usage of lead-free solders and components in electronics manufacturing, including researchers, design engineers, manufacturing engineers, quality assurance and materials and safety personnel as well as the management in implementing manufacturing strategies through a general understanding of lead-free electronics and solder joint reliability issues.

About the Instructors

Professor Jorma Kivilahti received his M.Sc. and D.Sc. degrees in Materials Science and Engineering from Helsinki University of Technology (HUT). After a few years´ period of research and development work in industry he returned to the university where he has been heading the laboratory of Electronics Production Technology as well as the Graduate School of Electronics Manufacturing, both in the department of Electrical and Communications Engineering at HUT. His R&D work covers new environmentally benign materials and the integration of electronics and photonics with low-cost manufacturing processes. In his scientific research the emphasis is on the physical and chemical compatibility of dissimilar materials controlling the reliability of electronics and photonics. He has published over 200 scientific and technological papers, possesses several patents in the field of electronics manufacturing, given numerous keynote and invited lectures and received several best paper awards with his colleagues in the fields of materials and manufacturing technologies. He is a member of the National Research Centre of Excellence in Tissue Engineering and Biomaterials. 

Dr. Tomi Laurila received his D.Sc. degree in electronics production technology from Helsinki University of Technology in 2001. The thesis has focus on the solid-state reactions in different metal/silicon systems and development of feasible diffusion barriers to be used in Cu metallized IC’s. At the moment he works as a research scientist in the laboratory of Electronics Production Technology. Presently his research involves the study of interfacial reactions between lead-free materials used in microelectronics assemblies. 

Toni Mattila received his M.Sc. degree in Materials Science and Engineering from Helsinki University of Technology (HUT), Finland, in 2000. Since then he has been working as a research engineer in the laboratory of Electronics Production Technology located in the department of Electrical and Communication Engineering at HUT. His research includes reliability of high-density electronics assemblies with the emphasis on lead-free assembly.

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