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Opening Session

SOC, SIP, and SOP: The Pros and Cons for Next-generation Convergent Systems

Professor Rao Tummala, 
Pettit Chair Professor and Director of NSF-ERC in SOP technology
Packaging Research Center
Georgia Institute of Technology

The SOP is an emerging microsystems paradigm that is beginning to be accepted as a complete system solution for the convergent systems of the next decade. Three other approaches offer options to these systems: 1) System- on -Chip (SOC) and 2) System-in Package (SIP) and MCM. In addition there are others such as quantum computing or molecular-electronics- based systems. The new and emerging molecular, optical and quantum technologies are considered at least two decades away from market introductions The SOC, while theoretically possible, presents fundamental, engineering, cost, investment and IP challenges. So it is viewed as a partial system. The MCM is viewed simply as interconnecting components and has been in use for almost 20 years. The SIP is being pursued aggressively by dozens of companies but as a 3 Dimensional stack of ICs or packaged structures, still requiring board additionally. The fundamentally -new SOP strategy is capable of bridging the time and technology gaps posed by SOC, by combining the best of on- chip integration, such as SOC, with the best of packaging integration such as SIP and multifunction board, not only with digital wiring but also with RF, optical and analog functions. It is expected to lead to microminiaturized and convergent microsystems with microelectronics, photonics, RF and MEMS-all integrated into a single- component systems. In doing so, it goes beyond MCM, Flip-chip, CSP and microvia technologies. 

This talk will present pros and cons of SOC, SIP, MCM and SOP. It will also highlight the status of SOP research at Georgia Tech and elsewhere.

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Assembly and Reliability of 3-D System-in-Package (SiP)

Eero Ristolainen
Tampere University of Technology
Electronics
P. O. Box 692
FIN-33101 Tampere, Finland
Phone: +358 3 3115 3390, Fax: +358 3 3115 2620, 
E-mail: eero.ristolainen@tut.fi

Electronics development has been driven mainly by IC technology progress. Cell size and line width have been continuously reduced, following the trend called Moore's law. This has created increasing pressure on the first level of interconnection. Up-to-now, these multi-chip packages or modules have only been used in low volume products. In general, this development path has provided size reduction in two dimensions, but packaging is a three-dimensional challenge. The first part of the 3rd dimension is tackled by reducing package thickness and also the standoff height. The next evolutional step comes through in the following ways: to grind extra sand away from active ICs, to use thin flexible substrates, and to stack the components. 
New concepts, such as System-In-Package (SiP) require novel dense packaging solutions to achieve small size and high operating frequencies needed to in today’s electronics. The stacked thin chip package developed in Electronics Institute of Tampere University of Technology is a promising miniature 3-D multichip package. Both thin chips and thin flexible substrates are used to achieve maximum reduction in both size and weight. The paste printed vertical interconnection bumps and solder bumped Flip-Chip seem to be the best alternatives to package assembly. Reducing the IC thickness below 100 mm creates new challenges for handling, interconnecting, electrical performance, reliability and design. These tasks are addressed in this study. 
In addition, the packages used for the tests are modeled and the correlation between the test results and the modeling is analyzed. The connection method to connect the module to outer world is a problem, which needs to be dealt. High accurate interconnection methods set challenges for the process control and manufacturing equipment. Devices are miniaturized to be more comfortable to carry together with increased functionality, have become drivers, especially for wireless devices. However, mobile terminal electronics have set a challenge for packaging and provided the motivation to verify emerging technologies. In addition, potential material and design options have selected by aid of FEM studies. Effect of die thickness, size and attachment method on various thin substrates has been analysed and results compared to tested ones. More details of the results will be discussed.

1] S. Pienimaa, J. Valtanen, Rami Heikkilä, and E. Ristolainen, Staked Thin Dice packaging, The 51st Electronic Components and Technology Conference (ECTC 2001), May 29-June 1, 2001, Lake Buena Vista, Florida USA, pp. 361-366.
2] Jokinen, E. and Ristolainen, E. 2001. Flip chip joining of Thin chips on Flexible PEN Substrate. Proceedings of IMAPS 2001 The 34th International Symposium on Microelectronics. Baltimore, USA, October 9-11. 2001, pp. 600-604.
3] R. Heikkilä, J. Tanskanen, and E. Ristolainen, Reliability Study of 3-D Stacked Structures, the 52nd Electronic Components and Technology Conference, May 28 – May 31, 2002, San Diego, CA, pp 1-5.
4] V. Kyyhkynen, J. Valtanen, R. Heikkilä, and E. Ristolainen, Thermal Compact Modeling of Stacked Multichip Modules, ScandTherm, First Scandinavian Conference on Thermal Management of Electronics, Stockholm, June 17, 2002, pp. 1-5.

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MP2  Flip Chip Processes

Chip-on-flex  -  The trends and possibilities in packaging

Søren Nørlyng
MICRONSULT
Denmark
Tel: +45 44651457
Fax: +45 44651458
noerlyng@micronsult.dk
www.micronsult.com

Chip-on-flex (COF) is seeing increased interest due to the market needs for denser and lighter products. Previously chip-on-flex was synonymous with TAB technology used for display drivers, but today very high volumes are seen in wirebonded IC packages. Also flip chips on flex have been introduced for IC packaging and furthermore expected in due time to replace the TAB “stronghold” for display drivers. The paper will give an overview of the different chip-on-flex technologies and in particular describe the various flip chip technologies with their respective bump types and joining techniques.

Adhesive technologies are extensively used and gold bumps- plated or stud bumped – are joined to the flex circuit with ICA (Isotropic conductive adhesive), ACA (Anisotropic conductive adhesive) or NCA (Non conductive adhesive). NCA’s are also used for solder bumps especially for smart card and ID-tag applications. NCA is an underfill variant, which is pre-applied. The preferred bonding method is thermode bonding and the characteristic cure/process-time can be extremely short. Recent development in NCA’s address compression gold-gold contacts and solder contacts. Applications with one or more chips on flex and Tape carrier Packages (TCP) – single layer, folded or stacked modules - will be reviewed, and the packaging trends utilising COF will be presented with reference to the activities at the largest packaging houses in the Far East currently having the largest COF activities.

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A Thermode Bonding Process for Fine Pitch Flip Chip Applications on Flexible Substrates

Barbara Pahl, Christine Kallmayer, Rolf Aschenbrenner*, Herbert Reichl*
Technical University of Berlin, Research Center of Microperipheric Technologies
*Fraunhofer Institute of Reliability and Microintegration IZM Berlin
Gustav-Meyer-Allee 25
D-13355 Berlin, Germany
Email: Barbara.Pahl@izm.fhg.de

Miniaturization is a key issue to achieve advanced performance of electronic devices and to decrease the overall cost of an electronic package. In this respect the flip chip technology provides excellent capabilities to meet the demands of recent and future requirements.
Solder joining is still the most common technology for flip chip assemblies. However a solder application by stencil printing can only be used successfully down to 200 µm pitch due to the solder paste and stencil features. Smaller solder volumes and new assembling processes are needed for finer pitches
In this paper a cost effective maskless bumping technique to create thin solder caps will be shown. Using a fast thermode bonding process chips with solder caps can be mounted on substrates. This work is focused on the assembling process of flip chips with pitches down to 40 micron on flexible substrates. The thermode bonding process for thin PbSn bumps with noflow underfiller is presented down to 40 micron pitch. The flip chip assembling process using electroplated AuSn bumps at 40 micron pitch will be shown.

The intermetallic phase formation plays an important role for the reliability of solder joints. Especially for a small solder amount the intermetallic phase formation can be very critical for further bonding processes and applications. The effect of the small gap due to the thin solder layer and the increased influence of the formation of intermetallic compounds on the reliability are studied. Results of reliability investigations such as thermal cycling and humidity testing are discussed.

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The Effect Of The Chemistry And The Filler Content Of Capillary Flow Underfill Encapsulants On The Flow Behaviour, The Thermomechanical
Parameters And The Dielectric Properties At High Frequency

Tony Winster, G. Luyckx
Emerson & Cuming, ICI Belgium N.V., Nijverheidsstraat 7, B-2260 Westerlo, Belgium
Tel. : +32 (0)14 57 56 11, Fax : +32 (0)14 58 55 30
tony.winster@nstarch.com, geert.luyckx@nstarch.com

Underfill encapsulants provide two functions. First, it protects the chip and the interconnects during subsequent processes, but second and more importantly, it improves the reliability of the interconnect system. These materials fill the gap between the chip or chip scale package (CSP) and substrate around the solder joints, reducing the thermal stresses imposed on the solder joints. The first generation underfill encapsulants were usually based on anhydride curing epoxy materials. More recently, as a result of potential health and safety issues with the use of anhydrides, a series of non-anhydride curing underfill encapsulants have been developed and commercialised.

Properties which influence the performance of an underfill are its thermal expansion coefficient and the elastic modulus. It is generally thought that an underfill material with a thermal expansion coefficient matched to the bump material and a higher elastic modulus are beneficial to optimising the fatigue life. In order to reduce the expansion coefficient, silica fillers are typically added to the epoxy resin. However, adding fillers will slow down the flow and increase the underfill time thus reducing throughput. This paper describes the effect of the filler content for both anhydride and non-anhydride underfill encapsulants on the underfill time as a function of the gap size and the temperature. The thermal expansion coefficient, the glass transition temperature and the elastic modulus as a function of the chemistry and the filler content are reported as well.
The dielectric constant and the loss factor at higher frequencies of respectively 1,8 GHz and 3,9 GHz for both anhydride and non-anhydride epoxy underfill encapsulants will also be presented for the first time.

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Bump & Assembly Technologies For Sub-100 Micron Pitch Flip Chip

Charles E. Bauer, Ph.D.
TechLead Corporation
2192 Augusta Drive 
Evergreen, CO 80439 USA
Ph (303) 674-8202 Fax (562) 268-9378 
Chuck.Bauer@TechLeadCorp.com

Wu Fei Jain
Chipbond Technology Corporation
Hsin Chu, Taiwan
FWu@ChipBond.com.tw

Excepting Au bumped tape automated bonded (TAB) liquid crystal display driver chips, the goal of sub 100 micron pitch flip chip remains elusive. Well understood advantages include die shrink opportunity as well as speed and performance enhancement. However, perhaps the greatest advantages lie in reduced substrate layer count (with accompanying cost reduction) and routing simplification leading to better impedance control capabilities. In order to cost effectively take advantage of these opportunities, fine pitch flip chip technologies compatible with both today’s bumping infrastructure and today’s substrate capabilities must be identified.

This paper compares and contrasts four alternative solutions for sub-100 micron flip chip bumping and assembly including traditional Au tape carrier packages (TCP), stud bump bonding (SBB) in combination with modern high density interconnect (HDI) substrates, Integrated Electronic Package Technologies’ (IEPT) plated Cu bump technology with traditional HDI substrates, and the very recently introduced Capillary Chip Connection (C3) from Microelectronics Assembly Innovations (MAINn). The paper and presentation include comparisons of bump and substrate/interconnect technical requirements plus a comparative cost analysis and a brief review of selected application examples.

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Poster Session

Actual Development in the Czech Electronics Sector 

Ivan Szendiuch, President IMAPS Czech and Slovak Chapter 
University of Technology in Brno, Faculty of Electrotechnic and Communication Technology, Department of Microelectronics, e-mail: szend@feec.vutbr.cz

There is significant increase of Czech crown position in the economical world. In the last six months increased the Czech crown from change 34,5 Kc for 1 € to 29,9 Kc for 1 €. One of the reasons is growth of foreign investments in Czech republic, where one part is created by electronic sector. There are today about 400 manufacturing companies in this sector, where about 60 % are foreign-owned.
Overview of research and development capacities, major investors and main producers, including some characteristics make the part of this paper as well as the territorial arrangement from the traditional point of view. The research and development system is presented with basic rules and general conditions, which offers good opportunity for collaboration with foreign subjects. Economical conditions in the Czech labour market are presented too. 
Electronic Sector Statistics 
· $4 billion sales 
· 400 manufacturing companies 
· 60 % of manufacturers foreign-owned 
· 8 % of Czech manufacturing output 
· 16 % of manufacturing exports 
· 120,000 employees 
· $1.5 billion foreign investment since 1990 
· 40 % of firms in Top 100 

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Point-to-Multipoint Transceiver in LTCC for 26 GHz

R. Kulke, G. Möllenbeck, W. Simon, A. Lauer, M. Rittweger
IMST GmbH
Carl-Friedrich-Gauss-Str. 2
D-47475 Kamp-Lintfort, Germany
Tel. +49-2842-981 214
Fax. +49-2842-981 499
kulke@imst.de
http://www.ltcc.de 

A point-to-multipoint transceiver module for 24.5 GHz to 26.5 GHz has been developed. Such a module is applied in public or private cellular networks known as LMDS (Local Multipoint Distribution Services). The recommendation T/R13-02 from CEPT/ERO has been utilized to design the circuits for its operation in terminal and base stations. The result is a very compact microwave multichip module with a 5 layer LTCC substrate, 12 GaAs MMICs mounted in stepped cavities, several SMD and hybrid components on the top, buried bandpass filters and optimised waveguide transitions. The T/R module is composed of a transmit (Tx), receive (Rx) and LO (local oscillator) path. These parts are shielded by using via fences through the substrate layers and metal walls in the cap. The module size is 61mm x 37mm including the aluminium housing. This development is a result of the European research project RAMP, which was running from 1998 until 2001. The design, assembly, characterization and evaluation has been performed by the authors, while Thales Microelectronics in France has manufactured the LTCC substrate and NMRC in Ireland the thermal management.

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Novel Stripline Coupler for Multilayer Ceramic Integrated Circuit (MCIC) applications

Sarmad Al-Taei, George Passiopoulos
Nokia Networks
Stanhope Rd, Yorktown Industrial Estate
Cambelrey, Surrey, GU15 3BW
Tel: +44 (0) 1276 602307
Mob: +44 (0) 7932 085489
Fax: +44 (0) 1276 602989
email: ext-sarmad.al-taei@nokia.com 

Practical Stripline implementations of couplers in Multilayer Ceramic Integrated Circuit (MCIC) technology incur a cost disadvantage when compared to an equivalent microstrip implementation. This is primarily due to the increased substrate thickness needed to achieve the required performance. Conventional stripline couplers significantly limit our ability to optimise for smaller substrate thickness, improved second level interconnect reliability, and overall cost. However, stripline couplers are needed for stacked integration scenarios and as building blocks for complex active and passive RF circuits in MCICs. A method of implementation that overcomes the practical disadvantages is therefore highly desirable.

This paper will present a novel stripline coupler structure that enable RF designers to utilise the stripline coupler achieving required levels of performance with much reduced substrate thickness. The paper will outline a structured design procedure and will present simulation and measured results confirming the validity of the technique.

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Microwave Circuits in Multilayer ORMOCER Thin Film

A multilayer sequential build-up structure for the integration of passive microwave devices is presented. The different devices were processed by using a photo-patternable polymer ORMOCER together with conducting layers of Cu on top of a FR-4 substrate. Microstrip and stub structures have been characterised at frequencies between 1 to 40 GHZ showing the feasibility of using this kind of material and build-up technology for microwave applications.

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Dispensing adhesive in narrow pattern using a multi-nozzle inkjet head

W. Voit ^a,c, M. Alsered ^b, K.V. Rao ^c and W. Zapka ^a
a XaarJet AB, SE-175 26 Järfälla, Sweden
^b MA Kapslingsteknik AB, SE- 163 56 Spånga, Sweden
^c Engineering Materials Physics Division, Royal Institute of Technology (KTH), SE-100 44 Stockholm, Sweden

The deposition of structured adhesive layers is an important step in the assembly process of many complex micro mechanical systems. A controlled dispensing of very small amounts of adhesives on predefined small joint areas is needed, while neighboring areas have to remain free from adhesive. In this work we describe the deposition of such adhesive layers using a multi-nozzle piezoelectric drop-on-demand inkjet printhead. The potential applications for this process are in the assembly of Micro Electro Mechanical Systems (MEMS), microfluidic biochip structures or optoelectronic components. 
The dispensing tests were performed with UV-curable adhesives with a viscosity of around 80 mPa·s at 25°C. A jet head with 126 channels and a printing pitch of 85µm, which can supply drop volumes of around 40 picoliter for a single droplet, was used for the dispensing process. The maximum achievable drop repetition frequency using this kind of adhesives was 3 kHz, allowing for a fast dispensing rate with a process time of less than 1 second for the deposition of an adhesive layer with an area of 25 cm² when using all 126 channels of the head.
Reliable dispensing of complex structures on silicon, glass or PVC substrates was demonstrated. Figure 1 shows a test pattern printed with UV-curable adhesive on a silicon wafer. The width of the dispensed lines was around 150 µm in this case. In figure 2 an array of single adhesive dots on a silicon wafer is shown to demonstrate the placement accuracy of the dispensing process. The analysis of a dispensed dot pattern on a silicon wafer, consisting of more than 10000 dots, gave an average placement error of 4 µm. The error in circularity of the dots was found to be less than 3 µm.
The dot- and structure-dimensions achieved with this technique depend on the type of dispensing head used, as well as on different rheological parameters of the adhesive and on the wetting behavior of the adhesive on the substrate. With 300dpi (dots-per-inch) inkjet heads we were able to achieve dot diameters of 150 µm on silicon wafers, and diameters of 100 µm and below on glass and plastic substrates. The dispensing of smaller and larger drop volumes is presently under investigation. The effect of this change in drop volume on the resulting dimensions of the dispensed structures will be presented.

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The Use of Infrared Imaging to Define Reliability in Assembly of ACA Flip-Chips Using Thin Substrates

Jalonen P., Määttänen J.*, Ekholm A., Reunamo P.
Satakunta Polytechnic, 
Tekniikantie 2, FIN-28600 Pori, Finland

*Elcoteq Network Corporation
Sinimäentie 8, P.O.Box 8, FIN-02631, Espoo, Finland

Anisotopically conductive adhesives (ACA) have emerged as an important joining technology in a number of significant application areas such as flat panel assembly and smart cards. These materials rely upon the trapping of conductive particles between the conductive pads and another part being locked by residual stresses to ensure retention of sufficient contact. No metallurgical interactions occur between pad and component in adhesive. In tests we qualified contacts using infrared (IR) thermal measurement instead of x-ray or laser. Relationships between ACA flip chip and the pads compared with solder lead, lead-free and the direct copper track connections in aging were considered in this paper. This paper presents the results from the reliability tests of different devices connected to the flexible in high density applications (pitch 200, 80, 54 µm). The contact resistances were measured with four-points-method using daisy-chain circuits by loading with different currents. Samples were tested using thermal shock test and 85/85 test. The generated temperatures were measured using infrared image processing.

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Concurrent Thermal and Electrical Analysis of Integral Resistors

H. Yu, D.Burlacu and J.K.Kivilahti
Lab. of Electronics Production Technology
Helsinki University of Technology
Otakaari 5 A, 02150 Espoo
Finland

High-speed, broadband, high performance telecom device manufacturing is placing increasing emphasis on reliable passive component integration. Unlike its SMT similitudes, there are potential concerns related to thermal management of integral resistors, because as being embedded inside boards it is more difficult for heat to dissipate out. 
The present work aims to analyse the thermal behaviour of integral resistors by employing a commercial thermal modelling tool and to provide necessary guidelines for thermal design of embedded resistors. Furthermore, the electric parameters (R, L, C) of the resistors are extracted and analysed and the high frequency behaviour is discussed by concurrent electrical modelling.
The resistors under consideration had two different resistances of 50 W and 100 W. They were manufactured with a build-up technique being developed recently in the laboratory into a FR4 substrate having one and four additional layers. Three sheet resistances 25, 100, 200 W/sqr were used. Width was varied in the range of 150 – 1000 mm to lower the power density and the influence of thickness of the multilayer structure was also analyzed. Steady state temperature distributions were first calculated with constant power of 0.25 W and then the accepted power was obtained by limiting the maximum temperature to the value of 130°C. The optimal geometry of the resistors were found out by comparing the results for different parameter combinations. Finally, the response of the resistor temperature to periodic power load was analyzed by the transient simulation for specific combination of parameters.
The electrical analysis was performed before and after the thermal analysis and the transmission and reflection coefficients were evaluated. The electrical parameters were extracted and the parasitic effects of the different shapes of the resistors were analyzed. To meet the broadband demands the simulations were performed in the frequency range of 500MHz - 40GHz.

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Connectionless Test (CT) using Electromagnetic signatures

Mahnaz Salamati, Dag Stranneby, 
EPE, Orebro University
SE - 701 82 Orebro, SWEDEN
dag.stranneby@tech.oru.se
www.tech.oru.se/epe

Today’s electronic products and subassemblies are highly integrated, miniaturized devices having complex functionality. Final test and troubleshooting using conventional test points, probes and bed-of-nails techniques are becoming harder, and are in many cases not even possible. Further, due to increasing production volumes, the time needed for testing is a critical factor. 

An alternative way to test a device is to employ Connectionless Test (CT). Using for instance standard EMC probes, the electromagnetic (EM) field surrounding the DUT can be measured (coherently or non-coherently) as a function of space and time, during different modes of operation. The recorded data of the EM field is matched to CAD data for the device, facilitating a mapping of features in the field to components and interconnects in the DUT. The so processed EM data is referred to as the Electromagnetic signature of the DUT.

Finally, the electromagnetic signature is matched to earlier signatures stored in an adaptive database being updated continuously. The database not only contains signatures from “known good” devices, but also signatures obtained from some typical failure types. In this way, the DUT can be classified as working properly, suffering from a previously known type of failure or having a “new”, hitherto unknown malfunction.

Since the electromagnetic signature also contains spatial information, it is an interesting tool in the troubleshooting process. Besides the type of failure, an estimate of the location of the problem may be extracted from the signature.

Initial practical tests have shown that the CT method outlined above works for both “analog” as well as “digital” electronic products having medium complexity. The aim of our present research in the area is to improve the method and to find the limitations in e.g. failure coverage and spatial resolution. Another interesting area being studied, is how to integrate the method in the manufacturing process to reduce the total time required for testing.

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TA1  RF and Microwave Packaging

A Novel Flip Chip Approach For Microwave/High Speed Data Chip Packaging

Tong Chen, Teledyne Technologies, Inc.

In recent years, Flip-Chip is becoming the major trend in packaging technologies as it offers both technical and manufacturing advantages over traditional wire bonding technology. Although Flip-Chip was originally developed for digital silicon chips that have high I/O counts, it also offers great advantages for microwave and high speed data applications. The bumps make much shorter connection than bonding wire, and have a well defined, repeatable geometry. All these features are critical to the packaging technology that dealing with higher and higher frequency, and large volume production. 
However, the Flip-Chip technology has not been widely used in the microwave and high speed data applications due to problems of conventional Flip-Chip methods. For example, conventional flip-chip did not consider controlled impedance at the connection. In order to do that, people use CPW structures, which have odd mode problems, require redesign MMIC, accurate placement, etc. Because most high frequency chips are made of GaAs with matching circuit on the chips, the under fill may substantially alter the performance by causing mismatch, and may damage the die mechanically. Another difficulty is thermal removal. This makes Flip-Chip more difficult for power devices. The exposed die needs a well sealed case, which adds costs. In some cases, the flipped die may radiate, a contribution to circuit instability.

Our solution tends to solve all the problems. First of all, our approach retains microstrip structure, i.e., a robust transmission line that microwave engineers familiar with. This allows the technology to be applied to virtually all existing dice. The heat is removed in the traditional way, i.e., from the back of the die. The heat sink also serves as a solid grounding to avoid common problems, including radiation from the flipped die. Meanwhile, the die is self sealed in the process. That eliminates further packaging requirement.

We have two approaches, both of which provided with the features mentioned above.
The first one is flip chip on substrates. This can be used for single chip packaging, but it is more suitable to create high performance, highly integrated “quasi-monolithic” MCM.
The second approach is flip chip in an injection molded plastic lead frame package. This is more intended for chip packaging. The goal is to achieve very low cost packaging without degrading performance.
Both approaches can be applied to any existing dice, from single FET to large MMIC. The approaches guarantee good thermal and grounding performance, and suitable for automation and high yield manufacturing. 

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The RF & Reliability Performance Ramifications of Suspended Ground Planes for BGA type LTCC Modules

George Passiopoulos, Kevin Lamacraft
Nokia Networks
Stanhope Rd, Camberley,
GU15 3BW, Surrey, UK
Tel: +44 1276 602985, Fax: +44 1276 602989
email: george.passiopoulos@nokia.com

The maximum recommended size/area of Ceramic BGA modules is typically limited by the thermal mismatch between the ceramic material and the module carrier substrate. This is more so the case with Low Temperature Cofired Ceramic Modules (LTCC) whereupon their 2nd level BGA Interconnect type reliability performance under thermal cycling has been observed to be inferior to Alumina based Ceramic BGA Modules when these are mounted on FR4 type substrates.

The relatively large size requirements of multifunctional BGA Type RF LTCC Modules aimed for Wireless Technology Infrastructure Applications in the 1-2 GHz range may then not be easily accomodated under such reliability constraints.

For a given set of BGA interconnect reliability compliance guidelines it is therefore highly desirable to investigate methods that enable a given module size. In this paper we propose and investigate such a technique, which is based on the concept of using suspended RF Ground planes which extend beyond the RF Ground BGA Interconnnection point. This technique enables a larger RF module size for a given BGA reliability level. So far there has been no clear understanding on the first order RF performance ratifications of the method. The proposed paper aims to adress this gap in the bibliography by means of a study using full wave EM Analysis simulations of a typical BGA type LTCC Module and to evaluate the range of applicability of the aforementioned technique.

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RF Benchmark up to 40 GHz for various low loss LTCC tapes

R. Kulke, W. Simon, C. Günner, G. Möllenbeck, D. Köther, M. Rittweger
IMST GmbH
Carl-Friedrich-Gauss-Str. 2
D-47475 Kamp-Lintfort, Germany
Tel. +49-2842-981 214
Fax. +49-2842-981 499
kulke@imst.de
http://www.ltcc.de 

LTCC multilayer ceramic has been tested in several RF applications in the past. The benefits are obvious: high level of integration, buried components, low losses, robustness and others. LTCC has been established in mobile communication techniques up to a few GHz like GSM power amplifiers and frontend modules or Bluetooth transceiver circuits. RF design engineers are discovering LTCC more and more for higher frequencies. Some examples are WLAN at 5 GHz, RADAR sensors for automo-tive at 24GHz or even at 77GHz and several frequency bands for digital radio networks operating from about 20GHz to 60GHz. However, the RF-behaviour of LTCC waveguides in the upper GHz-range has barely been tested. The industry is missing a comparative test between various LTCC substrates. Therefore the consortium of the German R&D project EASTON, funded by the German Ministry of Education and Research (BMBF) and managed by the German Space Agency (DLR), decided to launch such a comparative evaluation of LTCC substrate systems up to 40GHz.

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Lumped and distributed element design for LTCC radio filters

Jens Müller
Micro Systems Engineering GmbH & Co.
Schlegelweg 17
D-95180 Berg/Germany
Phone: +49 9293 78 64
E-Mail: jmueller@mse.biotronik-erlangen.de

Claude Guichaoua
Solectron Brittany/France
Route de Quimper
F-29590 Pont-de-Buis/France
Phone : +33 2 98 81 33 04
E-Mail : ClaudeGuichaoua@bty.slr.com

In the perspective of the 3rd generation of mobile systems (3G) and in the current evolution of 2G, multi-mode wireless terminals are developing to provide more services for users. Modes of interest are GSM 900, GSM 1800, IS95, TETRAPOL, TETRA, WB-CDMA, APCO 25, DIIS and GPS.
Very tight technical requirements (TETRAPOL, APCO 25), along with integration constraints (multi-mode capability in a user-friendly cabinet) and price pressure (-10% a year), make the new Platform a challenge. In that context, smart implementation of wide-band VCOs and tuneable filters are compulsory to meet market requirements.
LTCC is a convenient technology for the manufacturing of band pass filters for a bandwidth of 380 MHz to 2400 MHz as required by radio telephony systems. This technology provides three major benefits:
- first, the ceramic nature of the substrate allows the implementation of resonators of significant quality factor;
- second, the hybrid assembly process allows the mounting of a variable capacitor and varactor diodes to provide the tuning of this type of filters as well as a BGA connection to the mother board;
- third, the implementation of embedded passive components like resistors, capacitors and coils, along with. the fact that this technology allows a multilayer design which is nearly unlimited (20 layer substrates have been already successfully manufactured), allows an outstanding level of integration
The paper demonstrates two approaches for LTCC filter modules – lumped and distributed element designs. The development of the lumped BGA-filter module started with the electrical filter design. After electrical optimisation on the schematic level (including feasability for integrated components) the elements of the circuit were analysed for size and layers required to make them in LTCC. Optimisation was focussed on the size of the filter package. The maximum layer count defined was 8. The best choice was a hybrid solution with a mix of soldered components on top of the package and embedded components. Components which would require a large area or too many layers to be integrated in LTCC were selected as SMDs.
The embedded components (capacitors and inductors) were designed based on equations developed earlier. Finetuning of the component performance including interference and coupling effects was made with electrical field simulation. 
Distributed filters were designed and optimised using a 3D electromagnetic field solver. These filters were not limited to 8 layers to allow a more flexible design. 
The demonstrators were realised with DuPont 951 material using silver pastes. Solder paste stencil printing was used for bumping. After SMD mounting, the filters were singulated and assembled on a test board. 
Finally, the results of the S-Parameter measurement will be discussed.

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TA2  System Packaging

µZ-F™ System-in-Package - The Next Generation Multiple Die Package Solution

Vern Solberg 
Sr. Applications Engineer
Tessera Technologies, Inc. 
3099 Orchard Drive, San Jose, California USA
Phone: 408-383-3614 (direct) Cell: 408-568-3734
Fax: 408-894-0768 
e-mail: vesolberg@aol.com


Companies attempting to achieve more functionality in a small space or to improve a product’s performance may consider the combining of multiple functions within a single die. To reduce risk, others have determined that mounting several, already proven die on a single interposer structure a better solution. System-in-Package (SiP) methodology is thought to be more practical, have less risk and usually ensures a faster time-to-market. Mounting several different die sizes and types on a common substrate plane is easy enough, however, it requires a great deal of surface area. If the devices are stacked on top of one another, the surface area can be reduced, but the package assembly process can be a challenge. Another issue is package height. If the die are the same size or near the same size, spacers must be added to clear the wire bond interconnect and the overall package thickness becomes excessive. 

To address the need for packaging multiple silicon die for the SiP applications, Tessera has developed a unique low profile stacking technique. The package technology adapts flexible polyimide film-base substrate material with one or two copper circuit layers. The flex-based mZ-F SiP is quite versatile and when stacked or folded, offers the smallest overall outline possible. The unique combination of materials and package assembly methodology enables the smallest package outline and the lowest profile single or multiple IC die package available. The smaller package size furnishes very close coupling between IC devices and allows a number of passive devices to be incorporated within the package as well. In regard to performance, when signal and ground conductors are engineered well, the line inductance can be significantly reduced, a critical concern for the newer generation of high-speed memory and microprocessors. 

The mZ-F package technology can enable a dramatic reduction in product size, improve operational performance and increase functionality. The paper and presentation will detail a number of multiple die package configurations developed by the company for portable and hand-held electronic consumer products and high-performance memory applications.

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Multi Substrate Modules – Cheap Solution for 3D Packaging

Ivan Szendiuch 1), Josef Sandera 2), Jaromír Bílek 3)
1, 3) University of Technology in Brno , Faculty of Electrotechnic and Communication Technology, Department of Microelectronics, 
e-mail: 1) szend@feec.vutbr.cz, 3) bilekj@feec.vutbr.cz, 
2) SMTplus CZ. Ltd., Czech Republic , email: sandera@smtplus.cz 

Recently, one of the research objectives has been the interconnection technique, which is able to ensure the production of 3D packages. Especially low cost solution seems to be significant for the production nowadays.
The construction of 3D structure can be generally divided into following categories:
1. Multi Chip Modules (MCM) are often placed on ceramic or organic substrates. The connection of 3D MCM structures to the main board is very often made with standard shape of leads respective to used technology. 
2. Multi Substrate Modules (MSM), which are based on the combination of different types of substrates as for example classical PCB and ceramic with thick film technology. 
There are two main technical problems to find reliable and economical solution. At first, it is the realization of the proper connection between substrates. At second, to eliminate stresses on the device due to mismatches in thermal coefficients of expansion (TCE) of used materials. It is also necessary to ensure a high thermal conductivity of the whole system and good electrical properties such as low parasitic parameters.
The paper deals with the realization of various types of connections between two or more substrates made by different materials. The work is focused on the connection with solder balls and with edge terminals. 
First experiments have been carried out observing the connection between the ceramic material (Alumina) and FR4. Problems have occurred with the stress on the connection due to mismatches between coefficients of the thermal expansion (CTE) of FR4 and ceramic materials depending on the different technological factors. Mathematical modeling (ANSYS) was used to observe and describe these physical phenomena.
All solutions prefer non-vacuum processes such as conventional THT, SMT and TF technologies to achieve low cost for the final solution.

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Wafer Bonding Technologies for MEMS Packaging

Katarina Boustedt, Katrin Persson*, Sofie Bohman*, Dag Stranneby 
Electronics Production Engineering, Örebro University, 
SE-701 82 Örebro, katarina.boustedt@tech.oru.se 
in collaboration with Ericsson AB
*IMEGO (Institute of Microelectronics in Gothenburg)

With the recent trends in microelectronics to move more and more towards incorporating MEMS (Micro Electro Mechanical Systems) structures, lowering the overall cost becomes vital. One major cost driver in today’s MEMS is the packaging. Many of the MEMS structures require some level of low pressure for full quality operation, and some may even need vacuum to function properly.
Different MEMS packaging strategies exist on the market and they can be divided into two different approaches. The first one protects the wafer temporarily during wafer scribing or dicing and the second one provides a permanent seal to the wafer through full wafer bonding before scribing and dicing. The latter, permanent methods allows for selecting very low cost packaging without hermeticity as a requirement, whereas in the temporary seal methods the seal is removed after dicing and the sensitive structures become unprotected again.
For the future it will become increasingly desirable to integrate MEMS and e.g., CMOS in one package. This can be achieved in many ways, such as side-by-side assembled MCMs, integration of MEMS and CMOS in one process, and certainly wafer stacking, a major trend in microelectronics. Side-by-side MCMs are used in products today, for example in accelerometers from SensoNor and Motorola. Wafer process integration has been suggested and developed by, e.g., Analog Devices, but carries with it severe limitations in yield. 
There are a number of different wafer bonding technologies described in literature. Among them are anodic, fusion, soldering and adhesive bonding. Most of these technologies bond a glass or silicon lid to a MEMS wafer. This paper will present various wafer bonding technologies. Pros and cons of the technologies will be discussed, along with their suitability for use in MEMS and CMOS integration by wafer bonding. Early results achieved in an on-going project at Imego concerning anodic bonding using screen-printed glass paste will be presented

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Packaging at the Wafer Level: Worldwide Trends and Applications

E. Jan Vardaman
TechSearch International, Inc.
4801 Spicewood Springs Road, Suite 150
Austin, Texas 78759
email: jan@techsearchinc.com

With demand for lower cost packaging and increased function in smaller areas, the electronics industry is experiencing a growing trend in manufacturing at the wafer level. Manufacturing includes the device fabrication, packaging, and in many cases testing. Increased activity at the wafer level includes the fabrication of bumped devices or other constructions, device encapsulation and molding, and fabrication of MEMs. Applications include consumer, communications, computers, automotive, and medical. This presentation details the major trends in wafer level packaging with a discussion of applications. Specific descriptions of products and processes are included. Issues such as test and assembly at the wafer level at discussed. Challenges to the growth of wafer level packaging are discussed. 

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Jetting Technology for Microelectronics

Horatio Quinones / Alec Babiarz /Christian Deck / Lian Fang 
Asymtek Headquarters
2673 Carlsbad CA, 92008, USA
hquinone@asymtek.com

Selective dispensing of fluid onto electronic packages without physical contact in a reliable and consistent manner seems a natural alternative to traditional mass transfer methods that are often invasive and lack consistency. With the advances and improvements in technology of the micro-electronic industry and the nano-electronic, the scale of components used has consistently grown smaller. This has allowed for more efficient use of resources (a silicon chip that once held hundreds of transistors now holds millions) and more convenient and consumer friendly products (palm sized computers compared to warehouse sized computers forty years ago). However, as advances lead to decreases in the scale of components, similar advances must be made in the production process in order to assemble these components. One method used in current printed circuit board assembly is attaching components to the board with a surface mount adhesive (SMA). A small dot of adhesive is placed between two pads. Passive components i.e., 0402 can be attached to the board by jetting small dots of SMA material. The component is then placed on top of the SMA. The SMA is then cured, fixing the component in place. When applying the SMA, it is vital that the adhesives not cover any part of the leads, as this may decrease the quality of the solder connection. As components decrease in size, so does the gap between the leads. It is therefore necessary for the size of the adhesive dot to decrease to the same degree as the components decrease. Current technology can produce dots of surface mount adhesive of approximately 20 mil diameter and roughly 0.03-0.04 ml volume. Anticipating the continuing trend in component scale reduction, however, predicts that dots in the 8-10 mil diameter range will be required. The experiment described in this paper attempted to reach this measure of dot size using SMA and silver epoxy materials. Small dot jetting has additional leading edge applications. The present work shows the capability of jetting material in volumes of about 3 nano-liters. The underfilling 3D-packages with small gaps that are required to accomplish thin packages, as well as the underfilling of small die present yet another challenge to the consistency and accuracy of dispensing processes. This paper addresses the underfilling of 3D stacked die by jetting material on die surfaces with small dot to accomplish gaps of just a few microns gap. 

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The First 147 Years of OptoElectronics

Dr. Ken Gilleo
Cookson Electronics
gilleo@ieee.org

Photonics deals with the practical generation, manipulation, analysis, transmission and reception of photons. We have been harnessing the photon for thousands of years to predict changes in the seasons and the many other results of astronomy - the oldest science. Photonics moved ahead when optoelectronics (OE) was added as a new subset in the 19th century. Optoelectronics really began with the telecommunications revolution of the late 1800’s when modulated light was decoded into sound using a selenium photoelectric for the FIRST wireless. But it was the introduction of the laser, a key OE device that delivered the technology that lets us surf the Internet and transact business electronically.

This paper will highlight the most significant OE events including the development of optical fiber and the deployment of photonics-based telephone systems that preceded the Internet. 

A comparison of solid-state electronics with OE will show the both industries use fundamentally similar principles for devices. One major difference is the choice of chemical elements for each domain. While electronics is based around silicon, OE uses almost half of the periodic table in to produce a myriad of complex structures that deliver the desired photoelectric effects. Thus, the difference is elemental.

The final section will deal with newer OE technologies, including VCSELS, MEMS-based aligners and MOEMS switches. We’ll conclude by examining the challenges and probabilities of having an optical IC in the future. 

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TP1  Reliability assessment

Novel Packages and Packaging Technologies for Use in Harsh Environments

Peter Frisk*, Kristina Hagelin, Mats Lindgren
Kitron Development AB, Mailbox 5060, SE-551 40 Jönköping, Sweden
*Phone: +46 36 559 40 80, Fax: +46 36 17 46 55, 
E-mail: peter.frisk@kitron.com

Today, the market for high performance electronic applications with increased operational features is growing rapidly. In order to fulfil these demands, new packages and packaging technologies are developed continuously. It is not common that the military industry, that has high product requirements, is introducing new technologies, but often selects mature technologies. Though, the military industry must be able to manage new packaging technologies in the future.
This paper presents a study made in collaboration between the major Swedish defence industry companies and was performed with the intention to increase the knowledge about novel packages and packaging technologies.
The work focused on studying the feasibility to use advanced packages and packaging methods for use in military applications. Suitable fine-pitch BGA packages that were expected to be interesting for the participating companies were identified. Then, various mounting processes for the components and encapsulations on different types of micro-via boards were evaluated. An MCM-BGA package with specifically selected materials was also included. Also, the design of micro-via boards was assessed and different laminates and suppliers of such were studied. The best production process for each company was then used to assemble test vehicles for accelerated environmental testing aiming at identifying the reliability. Both temperature cycling and damp heat tests were performed. Thorough analysis methods such as microfocus x-ray, SAM and microsectioning have been valuable tools in assessing the results.
The results from the different tests show that the use of both fine pitch BGA’s and MCM-BGA’s on micro-via boards are very suitable for applications in harsh environments, but that a qualification for each application might be needed. The performed tests also show that underfill should be used for different fine pitch BGA’s. Other critical parameters are choice of solder paste, stencil design and stencil printing parameters.
The project conclusion is that very valuable knowledge and experience has been gained for the future regarding new component types, PCB design, PCB suppliers, assembly processes and analysis methods. It was also a sufficient way of studying the feasibility of different packaging technologies to fulfil specific requirements. This has been possible by the wide participation among the Swedish defence industries, the close collaboration and the wide experimental matrix that was used.

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On the Selection of Die-attach Materials for High Temperature Electronics

Frøydis Oldervoll, Morten Berg, Jon Nysæther¹ , and Frode Strisland
SINTEF
Department of Instrumentation and Microelectronics
Forskningsveien 1, NO - 0314 OSLO, Norway
Froydis.Oldervoll@ecy.sintef.no

¹ IDEX ASA, Gamle Borgenvei 5, Postboks 519, NO-1373 Asker, Norway

SINTEF develops instrumentation systems where both high temperatures up to 200 °C and large temperature variations can be expected. The purpose of the present work has been to find a reliable die-attach process for electronics intended for such harsh conditions. Different silver-glass and silver-filled polymer die-attach materials were used to attach silicon test chips to alumina substrates. The packages were subjected to 1500 temperature cycles from 0 – 200°C. The test chips, which have been developed by SINTEF, have temperature-sensitive diodes integrated that were applied to measure the thermal resistance through the adhesive. These measurements were used to monitor the die-attach quality non-destructively during the temperature cycling. Results of mechanical shear-stress tests done after the cycling was completed will also be reported. 

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A Characterisation of Plastic Core Solder Balls for BGA and Flip Chip Applications

Matthias Klein, Hermann Oppermann, Steffen Behnke, Rolf Aschenbrenner, Herbert Reichl
Fraunhofer Institute of Reliability and Microintegration IZM Berlin
Gustav-Meyer-Allee 25
D-13355 Berlin, Germany
Email: Matthias.Klein@izm.fhg.de, 
phone: +(49) 30 464 03-612, fax: +(49) 30 464 03-161

A plastic core solder ball consists of a large polymer core coated with a Cu layer which is covered with eutectic and/or high melting PbSn solder. The main advantages of such a system are higher reliability due to the relaxing of stress by the polymer core and a defined ball height after reflow. These balls could be an alternative method as bumping technique besides stencil printing and the use of preformed full metallized solder balls.
In this paper the results of the characterisation of plastic core solder balls will be presented. As test sample LTCC carriers with BGA contacts and daisy chain structures together with appropriate PCB boards were designed and manufactured. The objective of this work is the development of standardized components for RF applications up to 100 GHz. Therefore, it is essential to create a well defined gap between carrier and board. Two techniques were applied, on the one hand bumping with polymer balls and on the other hand a standard process with high melting PbSn solder performs as spacer.
The assembled and reflowed plastic core solder balls itself were investigated by shear tests and analysed using x-ray and SEM as well as EDX. Thermal cycling tests were performed with the assembled modules to get information about the electrical and mechanical properties of plastic core solder balls in comparison with standard techniques.
In addition, tests were carried out to use plastic core solder balls with a diameter of 100 micron for flip chip bonding of Si chips on PCB boards.

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TP2  Pb-free and Other Environmental Issues

Outlining Opportunities of Engineering Processes and Technology on Environmental Impacts of the End of Life Treatment of Mobile Terminals

Roope Takala (MSc. Tech.) and Pia Tanskanen (Lic.Tech.)
Nokia Research Center
roope.takala@nokia.com

Upcoming legislation on electronics waste in Europe will set new formal requirements for end of life (EOL) processes. Namely these include producer responsibility on obsolete product collection, pretreatment and recycling. A structure is needed for the complex environment of interactions between technical, environmental, socio-economic and legislative factors in take-back and EOL treatment. The complex EOL system can be divided into three distinct stages with different characteristics and stakeholders. The first stage is the organisation of the collection process. The second is the structural pretreatment and fragmentation of the product. The third stage is the recycling processes of the product material content. In this paper we propose a simplified economic and logistical model for an EOL process for mobile terminals. Based on this model we propose and demonstrate via example, both technical and engineering process driven possibilities in promoting economic implementation of the EOL processes. 

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Results of Life Cycle Assessments of EEE Using Generic Models for Products and Components

C. Herrmann, P. Eyerer
IKP
Abt. Ganzheitliche Bilanzierung, Boeblinger Strasse 78, D 70199 Stuttgart, Germany
Phone +49 711 6412265, Fax +49 711 6412264, E-Mail: herrmann@ikp2.uni-stuttgart.de

The environmental issues of electric and electronic equipment (EEE) are very complex and difficult to assess. Many aspects have to be considered, e.g. the design of products, the use of materials, the multitude of different materials, the properties and environmental behaviour of materials, the efforts for and during manufacture, the product structure, the product performance during use or the end of life situation (take back, re-use, recycling, recovery etc.). Thus, undoubtedly an entire life cycle perspective is a must, if the environmental behaviour of products and product systems will be considered comprehensively and by avoiding the shift of ecological burdens to other life cycle phases through the improvement of only one aspect.
The fundamental method to quantify environmental effects considering the entire life cycle, i.e. material extraction, energy provision, manufacture, use and end of life, is Life Cycle Assessment (LCA). Today, it is often applied in industry and serves as an ecological base information, which other methods can be build up or rely on, such as Design for Environment (DfE), risk assessments, recycling strategies and many more.
But one major problem still is the consistence of a very complex product structure and the diversity of applied components at EEE. The thematic field of “how to environmentally assess electronics” often fails due to missing data, knowledge of manufacturing or insufficient and inflexible assessing models for these products. 
Thus, this paper will present the modelling of electronic products for LCA. The so called Generic Module based LCA enables the user to model nearly all electronic products relating to their respective manufacturing phases. A short introduction to the method will be underlined by several examples. From the co-operation with industry partners outcomes of different multi-client studies will be shown dealing with LCA results of IT products and electronic car appliances. Taking into consideration mainly their manufacturing phase and the use phase it will be presented how LCA results can be calculated easily and how the respectively gained environmental information from these assessments can be used for product improvements.

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Microstructure Investigation of Sn-Ag-Based Lead-Free Solder Joints by Electron Microscopy

L. L. Ye¹, Z. H. Lai², J. Liu² and A. Thölén¹

¹. Department of Experimental Physics, Chalmers University of Technology, S-412 96 Göteborg, Sweden
². Department of Electronics Production, School of Mechanical Engineering, Chalmers University of Technology, S-431 53 Mölndal, Sweden

It is widely anticipated that the use of lead will be restricted in electronic solders in the near future because of its toxicity. In theory, many solder alloys could replace eutectic or near eutectic Sn-Pb solder in electronic assembly. The Sn-Ag system has limited solid solubility of Ag in Sn, making it more resistant to coarsening. As a result, Sn-Ag based alloys form more stable, uniform microstructure that is more reliable.
The present paper contains three parts of work related to the Sn-Ag-X system:
1) The influence of B on distribution of intermetallics in Sn-3.5Ag-0.5Cu alloy,
2) Interphases characterization between Sn-3.5Ag-0.5Cu lead-free solder and Au/Ni/Cu layer metallization, 
3) Coarsening of Sn-Ag-based solder joints during thermal cycling.
Ag3Sn and Cu6Sn5 are well defined precipitates in Sn-3.5Ag-0.5Cu solder alloy. With the addition of B, the Ag3Sn phase tends to be spherical, instead of forming lamellae microstructure in Sn-3.5Ag-0.5Cu alloy. At the same time, the distribution of Ag3Sn particles is more homogeneous. This is considered that the introduction of B provides more nucleation sites during solidification and therefore refines the microstructure.
Usually it was regarded that the interface between Sn-Ag-Cu alloys and Ni plated layer is mainly composed of Ni3Sn4. However, based on our study by using transmission electron microscope (TEM), the interphase is (Ni,Cu)3Sn4, in which the concentration of Cu is as high as 28 at.%. On the other hand, the crystal structure of this phase is the same as Ni3Sn4. Among (Ni,Cu)3Sn4 phase, even (Cu,Ni)6Sn5 particle was detected. So there are two phases formed at solder/substrate interface.
The results on the microstructure evolution of Sn-3.5Ag, Sn-3.4Ag-3.0Bi and Sn-3.2Ag-0.5Cu solder joints in Pb-coated lead frame show the obvious microstructrual coarsening effect. It is suggested that a small amount of Pb dissolved from the lead frame caused the formation of Pb-rich phase. Such phase has little resistance to coarsening, especially with Bi, for the ternary Sn-Pb-Bi liquid phase could be induced during thermal cycling. Compared with Pb-Sn solder joints, the shear strength of lead-free solder joints has little change before and after thermal cycling.

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Effect of PWB Coatings on the Reliability of Pb-free CSP Assembly

T. Mattila and J. K.Kivilahti
Lab. of Electronics Production Technology
Helsinki University of Technology
Otakaari 5 A, 02150 Espoo, Finland

The anticipated shift to lead-free electronics production may have unexpected impacts on the reliability of electronics. One of the main reasons for growing reliability concerns is related to large number of new lead-free material combinations, the metallurgical compatibility of which are not yet known. Among the lead-free solders the eutectic Sn-Ag-Cu and Sn-Ag-Bi fillers are most popular. When these alloys are in contact with the most common lead-free HASL alternatives, especially electroless nickel immersion gold (ENIG) or OSP-on-Cu, at upper reflow temperatures the solder joints become multicomponent alloy systems, where intermetallic reactions and microstructures are difficult to predict on the basis of the Sn-Pb metallurgy. 

In the present study, SnAgCu-bumped CSP components were reflow-soldered with the SnAgCu solder paste on Ni(P)|Au-, OSP- or Bi-coated multilayer PWBs and the assemblies were subsequently inspected and tested in thermal cycling. The test data were statistically analyzed using the Weibull method and the characteristic life times (η) and the shape parameters (β) were calculated. Statistically meaningful differences were found between the parameters for different coating materials. The failure modes were studied to reveal the relationship between the different β-values and the failure mechanisms and the results are presented and discussed in the conference.

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Anisotropically Conductive Adhesive: An Alternative for Soldering of Small Size Components in Volume Production

Jarmo Määttänen, Petteri Palm, Pasi Perttula,N.N.. 

Elcoteq Network Corporation
Sinimäentie 8B, P.O.Box 8, FIN-02631 Espoo, Finland
+358-10-41 311, fax +358-10-41 31 554
jarmo.maattanen@elcoteq.com, petteri.palm@elcoteq.com, pasi.perttula@elcoteq.com 
http://www.elcoteq.com

In electronic manufacturing business there is increasing need and also requirements for lead- and halogen free green technology. Target of our research was to develop low temperature interconnection method to replace the soldering as an interconnection method for high volume, small size passive and active components. The typical application areas are smart cards, smart labels, led stripes and small size flexible modules.
Since the usage of lead free solders means also the increase in process temperature problems will rice especially with sensitive components. So the lower process temperature is needed and therefore the cheaper base material can be used. One possibility is to use anisotropically conductive adhesives. The drawbacks are that the pressure is needed during the bonding process and longer bonding time for the curing of the adhesive. So new concept is needed to make the assembly. Therefore the fully automatic reel to reel manufacturing process is developed to achieve the mass production needs.
In this work the automatic assembly line for passive components using anisotropically conductive adhesive will be presented. The process temperature is limited to 180 °C and the process time for one component is reduced to one and a half second by using a special multihead bonding. The process control is concentrating to the alignment and the adhesion measurements of the components. The reliability of the process is ensured with the environmental tests.

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WA 1  Advanced board technologies

Implementation of solid metal bump interconnection technology for high
density interconnection and thermal management

Martin Valfridsson
Manager Technical Support
Clover Electronics Co., Ltd.
Phone: +46 70 273 7731
Fax: +46 70 8600 474
E-mail: martin.valfridsson@cloverpcb.com

Clover Electronics Co., Ltd in Japan has implemented a technology for high
density interconnection using solid metal bump interconnections of any
desired shape. Today's manufacturing specification realizes 0.1 mm pad with
0.1 mm capture pad and 0.2 mm pitch. The technology has also been proved to
increase the thermal conductivity of a printed wiring board. The paper
explains the manufacturing process, design considerations, reliability
tests, tests with embedded passives and results from field applications.

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The Importance of Characterizing Parameters in Galvanic Process of PCB Manufacturing

Teija Uusluoto, Paavo Jalonen*, Lenita Koskinen, Aulis Tuominen
Pori School of Technology and Economics
Tampere University of Technology
Pohjoisranta 11, P.O. Box 300, 28101 Pori
*) Satakunta Polytechnic
Tekniikankatu 2, 28600 Pori
tuu@pori.tut.fi

Miniaturization of electronics means finer lines and smaller vias in PCBs which increase the demand for more detailed and stricter supervision on circuit board manufacturing processes. A research project concerning the manufacturing techniques of high density printed circuit boards is presently going on at the Pori School of Technology and Economics. This study is a part of this project. 

This part of the project concentrates on electrolytic copper plating, a complex process chain including pre- and post-treatments. A well designed and properly constructed plating system, correct operating conditions and bath compositions are a prerequisite for successful plating. The plating process has a large number of parameters. It is necessary to select the correct parameters for process control in order to achieve high quality plating and trouble-free production. 

The purposes of this study are to determine the influence of increased aspect ratios on process design and process control. What are the issues on galvanic process which require more investigation? This work also gives us background information for the planning of the experimental part of high density PCB research concerning copper plating. 

Wide practical information about copper plating processes used in PCB factories was collected by means of interviews. Questions dealt with technical solutions, chemistry, parameters in process control, problems which appeared in plating or in monitoring. 

This report contains a brief survey of earlier studies and relevant literature about electrolytical copper plating and a summary of views of experts in this field. In addition, this study explores the mechanical properties of various copper platings.

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Manufacturing of Flexible Integrated Module Boards

T.F. Waris and J.K.Kivilahti
Lab. of Electronics Production Technology
Helsinki University of Technology 
P.O.Box 3000, 02015 TKK, Finland

In this communication a fabrication process for flexible integrated module boards (IMB) is presented. The IMB-technique being developed at Helsinki University of Technology enables very high density integration of active and passive components into organic substrates. Thinned active components (50 mm) were integrated into the flexible substrate using elastic molding polymer. Electrical interconnections were fabricated with the fully additive solderless process, where liquid photoimagible polymer was used as dielectric layer and high density wirings and interconnections were produced using electroless copper deposition. Since the module consists of flexible elements the resulting structure provides enhanced operational reliability. Flexible modules and their interconnection structures have been characterized in detail by using the optical and scanning electron microscopy and the major results together with the electrical test data are presented in the conference. This study was executed as a part of the EU-supported project “Flex-Si”.

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Status and future of HDI PWBs 

Tarja Rapala-Virtanen,
Development director, Aspocomp Group, Finland

Higher packaging density for the next generation of electronic devices require the utilization of inner space of a PWB for component placement. Aspocomp has been manufacturing HDI PWBs at Salo for more than five years. The chief focus has been on increasing packaging density and on accommodating the needs of future chip packages. In volume production, cost and performance have to be balanced. As a result, manufacturing and material yields, process automation, the cost of materials and added value technologies like embedded passives are key considerations in meeting the high volume requirements of the marketplace.

This paper will describe how these parameters have evolved over time and how it has been possible to achieve the stringent tolerances required in both the manufacturing and assembly processes.

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The Characterisation of Integrated RF Passive Components in LTCC

Antti Vimpari
VTT Electronics, 
P.O.Box 1100, FIN-90571 Oulu, Finland
Tel. +358 8 5512257, Fax. +358 8 5512320, 
Email: antti.vimpari@vtt.fi

LTCC-Technology enables the integration of passive components into the substrate of the electronic device. That could be used for the cost reduction by replacing discrete components. In this paper the focus is in inductance and capacitance realization for the functional frequency range up to 10 GHz. After designing, manufacturing and measuring different test structures it was obvious that the spiral inductor is still a very good structure for inductor realizing in the matter of the Q-value at the parallel resonance frequency and achievable inductance vs. used substrate area. For capacitor realization it was found out that interdigital capacitors of three fingers type were most likely to act in the desired way. A great number of spiral inductors and interdigital capacitors of different geometries were manufactured and measured to find out the useful frequency span and the optimal dimensions. The tests were repeated by using different commercially available LTCC material systems. The measured peak Q-values for the spiral inductors were up to 100. The lowest measured insertion loss for the three finger interdigital capacitor was 0.4 dB at 7.7 GHz (the series resonance frequency of the capacitor).

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WA2  Ceramic high performance materials

Properties of High Definition Photoimaged Conductors in LTCC

Kari Kautio
VTT Electronics (http://www.vtt.fi)
Kaitoväylä 1, 90570 Oulu, Finland
E-mail: kari.kautio@vtt.fi

Low Temperature Co-fired Ceramic (LTCC) technology is a multilayer ceramic process, capable of high packaging density at low cost. Other key benefits of LTCC - high layer count, controlled dimensions and low loss materials give the ability to build interconnect substrates and modules with integrated passive components for high frequency applications. There is a growing interest in new LTCC systems for microwave frequency applications due to the development of low loss dielectric materials and advanced conductors and the possibility to realise 3D controlled impedance lines and structures for EMI shielding by using ground planes and via fences. Conventional screen printing of conductors is normally used, with the limitation of minimum line width and spacing to about 100 mm. Smaller feature size will be necessary for certain designs at microwave frequencies. Photoimageable or photosensitive thick film conductors, capable of 50 mm line resolution and improved line edge definition, allow the fabrication of high performance microwave structures. In this paper, the general processing aspects for co-fireable photoimaged Ag conductors are described. The dimensional tolerances of photoimaged conductors are characterised and their suitability for high frequency LTCC applications evaluated.

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Photoimageable Thick Film Implementation of Very High Density Ceramic Tehnology Products

Valentinas Baltrusaitis and Jurate Minalgiene
Hibridas JSC
271 Savanoriu Ave
LT-3009 Kaunas
Lithuania

Tel.: +370-7-774-221
FAX: +370-7-312-833
Email: hibrid@lira.lt

The functional integration and miniaturization are predominant for all microelectronic systems. Different technological approaches are available to achieve high density structures focusing on greater miniaturization of components and subsystems. Generally they are based on improvements of existing technology, including ceramic substrate thick film technology, which offer solutions that are cost effective and completely applicable for today needs. Evolving of this technology towards higher integration densities resulted in photoimageable thick film process based on innovative photosensitive materials systems. There is a need to publicize the capabilities and benefits of this processing method.

Analysis of possible technological limitations to achieve the most effective use of photosensitive inks and UV-patternable thick film process is presented. 

Limits and possibilities of photoimageable silver and gold conductors and photosensitive dielectric are discussed as basis for high density multilayer interconnection structures and microwave systems. 

The emphasis is made on very little known photosensitive materials-silver palladium conductor, platinum based compositions and ruthenium resistors. These materials are key to high density passive integration and miniaturization in some very special areas of application including thick film sensors. 

The paper presents photoimageable thick film process as implementation of special high density devices–multilayer high density interconnection structures, multilayer miniature microwave devices, resistive circuits, platinum and gold structures for sensors in aspect of especial requirements and high density solution.

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Generic investigation on 0-shrinkage processed LTCC

Michael Hintz, Heiko Thust - Ilmenau Technical University, Germany
Heiko.Thust@E-Technik.TU-Ilmenau.DE
Erich Polzer – DuPont, Germany

Free sintered LTCC substrates are often assessed in their dimensional accuracy concluding that the overall x/y-shrinkage and tolerances at sintering may account for component assembly problems. The tolerances effect increases with size of the produced substrate. The geometrical accuracy and substrate flatness are of importance to fine-pitch mounting processes especially with mouldings and cavities.

The paper describes results of our investigations concerning the shrinking behaviour of substrates made out of different tape materials, Du Pont 951, at various layer counts by using release tape 953A6 following the pressureless and pressure assisted sintering (PLAS and PAS) procedure. Even results are available for single side usage of release tape.

In the standard zero shrinking technology the substrate material is cofired within layers of release tape. Outer conductors are then applied as postfire prints. Cofiring surface conductors is possible; however, the release tape will influence their sintering behaviour followed by performance in bonding and/or soldering. Important is the characteristic of the release tape and the method for removing it after sintering. Results of our investigations with cofired silver conductors are explained. 

The usefulness of release tape and zero shrinking technology for cavity formation is shown. Use of a modified uniaxial lamination technology in combination with release tape leads to improved process technology of cavities manufacturing.

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HeraLock^TM 2000 Self-constrained LTCC Tape - Benefits and Applications

Peter Barnwell, Edmar Amaya, Frans Lautzenhiser, James Wood, 
Heraeus CMD
24 Union Hill Road
West Conshohocken, PA 19426-2736, USA
pbarnwell@4cmd.com

Low Temperature Co-fired Ceramic (LTCC) is finding greatly increased application in fabricating circuits for many applications. Wireless, microwave, photonic and automotive applications are all growing. The advantages of parallel manufacturing, short time to market and the robustness and stability of ceramic are all advantages for these applications. Unfortunately, the shrinkage on firing of LTCC can cause problems in some applications, as well as leading to a reduction in available circuit area.

HeraLockTM 2000 tape exhibits near-zero shrinkage (0.08% +/- 0.05%) in the x and y directions upon firing. This minimal shrinkage with very tight dimensional control is achieved without the use of external constraints such as removable layers or mechanical clamps. The unique properties of this tape system have several performance enhancing and cost reducing benefits due to process simplicity that allows for an increase in the overall yield. Furthermore, the tight shrinkage control of HeraLock TM enables an increase in the LTCC panel size, allowing for further reductions in individual module cost as well as simplifying high volume manufacturing. 

HeraLockTM 2000 is a lead and cadmium-free formulation with properties appropriate for RF applications requiring high performance at frequencies up to at least 6 GHz; automotive modules and general-purpose packaging. Supporting these applications is a material set of conventional tape, co-firable conductors including silver routing and 100% coverage ground plane silver formulation, a via-fill and a silver-platinum solderable top conductor. For higher frequency microwave circuitry, Heraeus KQ materials can be post processed on HeraLockTM giving precise geometry conductors and ultra low loss dielectrics.

The resulting novel RF platform approach will be discussed, of particular interest being the ability to incorporate 100% coverage ground planes and cavity structures. For optoelectronic applications, it is possible to incorporate buried optical channels and fibers which remain undistorted after firing. 

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The development of a new system of materials for AlN substrates

Y.L. Wang, A. F. Carroll, J.D. Smith, Y. Cho, R.J. Bacher, D.K. Anderson, J.C. Crumpton , C.R.S. Needes, DuPont I-Technologies, RTP; USA;
J. Cocker, J. Ferguson, Du Pont U.K., Bristol;
G.Vanrietvelde, DuPont France, Les Ulis. 

Substrates exhibiting high thermal conductivity have always been in great demand, particularly for automotive and industrial applications, for their ability to dissipate heat in small volume, enabling the fabrication of miniaturised power circuits.
A number of different solutions to tackle the heat dissipation of power circuits have been considered, including design techniques, although the usage of thick film with thermally conductive substrates such as BeO and, more recently, AlN, have proven to be the most cost effective. Nevertheless, for health and disposal concerns the use of BeO has become restricted, leaving AlN substrates as the most challenging alternative.

This paper will discuss a thick film system consisting of conductors, dielectric and resistors developed specifically for use with the most likely alternative, AlN substrates. 

The challenge that AlN presents on the development of materials to be applied and fired onto it, is its reactivity. Under normal firing for most thick film materials conditions (air, 850°C), AlN will reduce frits and binders containing Pb, Ru, Bi and Cu, producing N2 gases. For this reason, conventional thick film materials working on Al2O3 substrates will either blister or exhibit poor adhesion to AlN substrates. A novel approach adopted by DuPont in the development of the new material system is the use of a reaction bonded binder system to promote conductor adhesion while minimizing gases produced at the conductor/substrate interface.

The presentation will cover the development of conductors having different metallisations, namely Au, Ag, Ag-Pt, Ag-Pd and Ag-Pd-Pt, and review their performance on AlN substrates, such as initial and aged adhesion, solderability and solder leach resistance. 

The system include also the development of fully compatible materials including a crossover dielectric and a resistor series with a range from 1ohm to 1Kohm/sq; resistor properties such as TCR, noise, blendability of adjacent members and refiring stability will also be part of this presentation.

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